Integrated circuit memories use various clock signals to control the timing of internal operations. The clock signals may be generated by clock circuits included in the memories, which may include delay line circuits to adjust the timing of the clock signals relative to one another. In generating a clock signal, an input clock signal may be delayed through a delay line circuit to provide an output clock signal having a delay relative to the input clock signal. The delay line circuit ideally provides an output signal that is a true version of the input signal, but delayed. However, due to imbalances in electrical characteristics of circuits included in the delay line circuit, the input clock signal may be distorted as it propagates through the delay line circuit to provide the output clock signal. For example, a delay line circuit including circuits having imbalanced electrical characteristics may introduce duty cycle error when providing an output clock signal.
Electrical characteristics of circuits may become imbalanced due to operating conditions to which the circuits are subject during normal operation. For example, particular ones of the circuits included in a delay line circuit may be subjected to operating conditions (e.g., voltage and/or current conditions) that cause degradation of the electrical characteristics for those particular circuits. Other similar circuits also included in the delay line circuit, however, may not be subjected to the same operating condition and consequently do not degrade to the same extent. Thus, the circuits of the delay line circuit, which in theory should operate similarly, degrade unevenly. The resulting performance of the circuits subjected to the operating condition may be different than the performance of the circuits not subjected to the operating condition. The difference in performance of the circuits may cause the circuits to distort an input signal clock as it propagates through the delay line circuit to provide an output clock signal. As known, a distorted output clock signal may significantly limit memory performance.